| Summary: | 碩士 === 淡江大學 === 電機工程學系 === 89 === This thesis describe a 3 bands PLL (Phase-Locked Loop), each channel have 3 channels. This PLL is implemented in UMC 0.5μm standard CMOS process.
In chapter 2 of this thesis, the basic theorem and operation of Phase-Locked loop will be introduced. And the sub-circuit will be introduced too; they include frequency-phase detector (PFD), charge-pump circuit, voltage-controlled oscillator(VCO), loop filter and frequency divider.
In chapter 3, we make the description of the high frequency CMOS prescaler. In this chapter, high-speed dual-modulus are discussed and implemented.
In chapter 4, we introduce oscillator theory, and several structure of VCO, they include ring, relaxation, and LC-tank oscillator. We also design and simulation a LC-tank oscillator which fits the specification of our requirement.
In chapter 5, we introduce all the sub-circuit of our work, and simulation all of these circuit. We find the power consumption is too large, so we improve the disadvantage of the previous version of this chip. The previous version of 3 bands PLL is that the power consumption is too large (about 160mW), so a new framework is adopted. In the new structure PLL, we use an additional divide-by-2 circuit to reduce the power consumption of pre-amplifier, which consume the most power of this chip.
Final, the implement of this chip use the UMC 0.5 μm mixed-mode CMOS process, total area of this chip is 400μm x 800μm. As it works at 3 frequency bands (921MHz, 864 MHz and 434 MHz) in 5V supply voltage, the total power consumption is 90mW.
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