| Summary: | 碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 89 === The switched-current digital to analog converter has the advantages of small chip size and low power dissipation compared with the other kinds of converters. Therefore, the proposed DAC in this thesis adopts this kind of architecture. Because usual switched-current D/A converters convert signals in serial-input way, their speeds are not pretty well. In order to improve this shortcoming our proposed DAC compromises between serial-input and parallel-input ways to speed up the conversion rate.
In this thesis, we design and implement a 10-bit digital to analog converter with TSMC 0.35mm 1P4M CMOS process technology. Basically, the switched-current D/A converter is comprised of a 5-bit weighted current source and a current divider by 32. The major difference between our proposed DAC and other switched-current D/A converters is that we adopt a new algorithm named combined-input algorithm. The algorithm first deals with 5LSBs(b1~b5) and then 5MSBs(b6~b10) by adding the preceding result of 5LSBs. This architecture presents the reduction of the number of transistors, chip size and power consumption. With the loads of 200W and 5pF to our proposed D/A converter, the simulation results show that our proposed switched-current digital to analog converter occupies an area of 0.35mm2 and consumes a power of 26.1mW with the speed up to 31.25MS/s.
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