Performance Driven Based on Signal Repeater Insertion for RLC Interconnections
碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 89 === While the process technology in VLSI manufacture gets into deep sub-micron, the interconnection wire delay for a chip performance becomes greater than gate delay. Reducing interconnection delay is an important objective for promoting system perfor...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/90438677012646857694 |