Performance Driven Based on Signal Repeater Insertion for RLC Interconnections

• Main Authors: Chih-Ching Yan, 顏志清
• Other Authors: Chia-Chun Tsai
• Format: Others
• Language: zh-TW
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/90438677012646857694

碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 89 === While the process technology in VLSI manufacture gets into deep sub-micron, the interconnection wire delay for a chip performance becomes greater than gate delay. Reducing interconnection delay is an important objective for promoting system performance. Usually, the interconnection delay calculation was based on RC model. But, the working frequency of a chip has promoted to GHz, obviously the inductance factor cannot be neglected again. Naturally, a second-order RLC model has to be considered in calculating the interconnection delay. In general, buses exist in a chip and their interconnection delay has influence on the circuit performance. Reducing the interconnection delay in buses can affect the chip performance. In this thesis, a greedy algorithm is proposed to reduce the propagation delay, given the topology of a multi-source multi-sink bus with the RLC delay model. The algorithm tries to insert a signal repeater into the middle of a segment that located on the critical path and adjust its sizes to minimize the maximum interconnection delay. The above procedure is repeated until no any improvement in delay reduction. Experiments exhibit to reduce the delay of 48%, 86.92%, and 62.63% in average for 0.18, 0.35, and 0.5micron technologies, respectively.