| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 89 === The short cycle spent for the design of digital circuits makes digital design very successful in the IC market. One important factor makes shorter time-to-market of digital circuits is the completeness of CAD tools. Lack of similar analog CAD tools, the design of analog circuits is a hard work and time-consuming. Even an analog circuit performs during simulation, an incorrect layout may make the circuit fail. The reason is that the layout of an analog circuit needs more accuracy model than a digital one.
In this Thesis, a new stacking algorithm for analog circuits was proposed. In this algorithm, the resistance and parasitic capacitance induced by interconnect, and process gradients are taken into account for archiving higher accuracy. In the past, most stacking algorithms of analog circuits did not take these factors that impact performance into account and so they are not accurate enough. We will review these algorithms and make comparisons with our algorithm.
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