A Novel Low-Voltage Content-Addressable-Memory Cell with a Fast Tag-Compare Capability Using PD SOI CMOS Dynamic-Threshold Voltage MOS Techniques

• Main Authors: Fu An Wu, 吳福安
• Other Authors: James B. Kuo
• Format: Others
• Language: zh-TW
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/36072672751535778328

碩士 === 國立臺灣大學 === 電機工程學研究所 === 89 === This thesis reports two low-voltage Content-Addressable- Memory (CAM) Cells with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques. In chapter 2, this thesis reports a novel low-voltage Content- Addressable-Memory Cell with a fast tag-compare capability using partially depleted SOI CMOS dynamic-threshold techniques. With two auxiliary pass transistors to dynamically control the bodies of transistors in the tag-compare portion of CAM cell, this SOI CAM cell has a fast tag-compare capability at low supply voltage of 0.7 V. In chapter 3, this thesis presents the leakage current of the CAM cell due to the floating-body effect of the PD SOI device and reports an approach using a p-type PD SOI MOS device with diode connections to dynamically control the bodies of access transistors of the CAM cell. Using this approach the leakage current can be eliminated effectively. In chapter 4, this thesis reports a novel low-voltage Content- Addressable-Memory Cell with a faster tag-compare capability using partially depleted SOI CMOS dynamic-threshold techniques. Using the advantage of the SOI techniques to decrease the operation voltage of the tag-compare portion of the CAM cell and using an auxiliary transistor to dynamically control the body of the discharge transistor of the CAM cell, the delay time of tag-compare can be reduced to the 44% delay time of the circuit reported in chapter 2 at 0.5-1.2 V supply voltage. The above-mentioned circuits are verified by the 2D MEDICI simulation program results.