| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 89 === In this thesis, a Reconfigurable Discrete Cosine Transform Processor with shape-adaptive capability for DCT-based video coding applications is presented. The Reconfigurable DCT Processor incorporates a general-purpose embedded processor system and an application-specific reconfigurable co-processor with DCT computation acceleration. The application-specific reconfigurable co-processor, which is called the Reconfigurable Discrete Cosine Transform Co-Processor, is a reconfigurable architecture that can perform standard 2-D 8 8 DCT/IDCT and both forward and inverse transforms of the more complex SA-DCT. Due to the integration of both hardware and software on Reconfigurable DCT Processor, this reconfigurable computing system can perform all DCT-based video coding applications including traditional frame-based video coding and arbitrarily shaped video objects coding of emerging multimedia applications in a more flexible fashion.
Two chip designs of Reconfigurable DCT Co-Processor are implemented using cell-based design flow. One is the core only design, and the other is the core with DFT consideration design for fabrication. The whole system of Reconfigurable DCT Processor is also verified by FPGA implementation based on Nios SOPC platform.
The proposed system architecture can be regarded as a basic platform, and different co-processors targeting functions other than DCT computation are also possible to be integrated into this system architecture.
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