Refunction Based Multipartition Architecture for Low Power Circuit Design

• Main Authors: Kun-Lin Tsai, 蔡坤霖
• Other Authors: Feipei Lai
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/19148104323212382435

碩士 === 國立臺灣大學 === 資訊工程學研究所 === 89 === Circuit partition for low power is one of the useful techniques which reduce power dissipation by confining the switching activity to a subcircuit. In this thesis, we propose a novel multipartition architecture to achieve low power dissipation as well as small area underlying global-encoding algorithm. Our synthesis flow consists of three phases: first we evenly partition the output patterns based on the Shannon expansion, second we encode the output vectors of each partition to build an equivalent functional logic, and finally we apply refunction algorithm to rearrange the logic function for reducing power and area. Experimental results show that our algorithm can obtain sizable power saving over a wide range of MCNC benchmarks. The power saving of up to 77.2% as well as 70.4% area reduction and average 50.1% power reduction with 38% area decreased have been obtained.