The Design of A 1.5V, 2.4GHz Fully Integrated CMOS Low Noise Amplifier
碩士 === 國立海洋大學 === 電機工程學系 === 89 === This thesis presents the design of a fully integrated 1.5V, 2.4GHz two-stage CMOS low noise amplifier (LNA) for RF front-end applications. No off-chip element is needed, for it is implemented all on-chip. A conventional cascode topology is used with som...
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| Format: | Others |
| Language: | en_US |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/39737756673246890312 |
| Summary: | 碩士 === 國立海洋大學 === 電機工程學系 === 89 === This thesis presents the design of a fully integrated 1.5V, 2.4GHz two-stage CMOS low noise amplifier (LNA) for RF front-end applications. No off-chip element is needed, for it is implemented all on-chip. A conventional cascode topology is used with some modification. Inductive source degeneration is used in the input-matching network to provide the 50 ohms impedance and for simultaneous matching of noise and power gain. The first stage of the LNA is the cascode LNA and the second stage is a buffer with some gain. An inter-stage matching network is added between the common-source transistor and common-gate transistor of the first stage to further lower the noise and enhance the overall gain and thus upgrade its performance. Inductor is used in this inter-stage matching network since the transistors are capacitive in nature. For the output matching network, it is matched the output to approximately 50 ohms. Using the Ansoft Harmonica as the RF simulator, the simulation results shown that the amplifier provide a gain of 20.81dB with a noise figure of 3.95dB while drawing 24.5mW from a 1.5V supply. The S11 and S22 are both lower than —15dB. This LNA is fabricated in TSMC 0.35um process.
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