| Summary: | 碩士 === 國立海洋大學 === 電機工程學系 === 89 === In this thesis, we design a low-voltage wide-bandwidth over-sampling Sigma-Delta analog- to-digital modulator. This modulator can be used in fully integrated and multi-standard RF receiver architectures, which require a high dynamic range analog-to-digital converter. We take multi- stage noise shaping with high order (4th order) and high over-sampling ratio (64 times) to improve the performance of the modulator. This architecture is mainly composed of a fully differential operated amplifier, a fully differential comparator, a non-overlap clock divider, a flash ADC, a voltage scaling DAC, and some digital logic circuits. Where fully differential switched-capacitor is used to implement the circuit of the modulator. The analog-to-digital modulator is designed to operate at 3.3 voltages with the signal bandwidth of 100KHz in baseband. The system sampling frequency is 12.8MHz, and the over-sampling ratio is 64. Also the signal-to-noise ratio and dynamic range are above 86dB for 14-Bit resolution. The total static power dissipation is 65mW, and layout area is 880um*1045um. The modulation circuit is implemented with the process of 0.5um 2P2M by UMC.
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