An Enhanced Built-In Self-Test Complier for Multiple Memory Cores in System-on-Chip

• Main Authors: Chia-Ming Hsueh, 薛家明
• Other Authors: Cheng-Wen Wu
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/20715425108954611631

碩士 === 國立清華大學 === 電機工程學系 === 89 === Memory testing is becoming the dominant factor in testing a System-on-Chip (SoC), with the rapidly growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SoC design. The BIST generation framework is a much improved one of our previous works. Test integration of heterogeneous memory architectures and clusters of memories are focused. An automatic test grouping and scheduling algorithm optimize the overhead of memory testing in test time, performance, power consumption, etc. The minimized BIST circuitry can deal with multiple memory cores including various types of multiple-port and single-port SRAMs. With configurable and extensible architecture, the proposed framework facilitates the overall test integration for core providers as well as system integrators among various design and test matrices.