| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 89 === The size and complexity of system chip make it imperative to accurately localize faults prior to any destructive analysis. Thus diagnosis is becoming an important issue in system-on-chip devel-opment. We propose diagnosis schemes for memory cores and logic cores separately. For memory diagnosis, a programmable built-in-self-diagnosis with an embedded address descrambler is pro-posed. With low hardware cost, the BISD circuit supports conventional fault models as well as neighborhood pattern sensitive faults.
For logic diagnosis, we propose an effect-cause methodol-ogy
based on simulation and traces error propagation paths from erroneous primary outputs toward error source. In addition, a ranking procedure is also proposed to reduce the time to locate the real defect. With this scheme, fault candidates can be localized within a small number and identified in a few steps.
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