A Test Processor for Memory and Logic Test in SOC Environment
碩士 === 國立清華大學 === 電機工程學系 === 89 === In this thesis, a bus-based test scheme is proposed. A Test Processor is the test source and sink and the existing on chip bus is the test access mechanism (TAM). The Test Processor behaves as a bus master or a bus slave. When it wants to apply test pat...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/17129279697058561613 |