A Test Processor for Memory and Logic Test in SOC Environment

• Main Authors: Hong-Ta-Hsu, 徐宏達
• Other Authors: Tsin-Yuan Chang
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/17129279697058561613

碩士 === 國立清華大學 === 電機工程學系 === 89 === In this thesis, a bus-based test scheme is proposed. A Test Processor is the test source and sink and the existing on chip bus is the test access mechanism (TAM). The Test Processor behaves as a bus master or a bus slave. When it wants to apply test patterns to or capture response from the circuits under test, it acts as a bus master. When it detects a fault during test, it stalls itself and stops requesting the bus access, and then acts as a bus slave. To reduce test time, the Test Processor has pipeline architecture and seven instructions designed for high-speed testing. The whole test scheme is suitable for high-speed memory and logic test. Compared with ARM processor, the test time is efficiently reduced. For memory test, the Test Processor can capture data from the on chip bus and compare it with the expected one in a pipeline manner. For logic test, it has dedicated LFSR and MISR hardware to generate the pseudo random test patterns and compress responses in one clock cycle. After seting values of loop counter, loop start address, and loop end address, the Test Processor can execute instructions in loop manner without extra overhead of loop control instructions, and thus reduce test time. In this thesis, two different test wrappers for logic with scan are also proposed.