| Summary: | 博士 === 國立清華大學 === 電子工程研究所 === 89 === When the thickness of MOSFET gate dielectric is scaled below 1.5 nm, the gate leakage current level will be unacceptable due to direct tunneling current. High dielectric constant materials can potentially be used as gate dielectrics for future deep submicrometer MOSFETs. In this thesis, metal/Ta2O5/metal capacitors, metal/ Ta2O5/silicon capacitors, MOSFET transistors and MOS gated diodes with Ta2O5 gate dielectrics were fabricated.
The electrical properties of the Ta2O5/silicon interface were studied by using MOS gated diodes with Ta2O5 gate dielectric. The generation current Igen, interface trapped charge density Dit, surface recombination velocity So and minority carrier lifetime in the field-induced depletion region t0FIJ of the Ta2O5 gated diodes were obtained.
The transistor properties were characterized. The ID versus VDS and IG versus VGS curves were measured. The Ta2O5/silicon barrier height was calculated by using both the lucky electron model and the thermionic emission model. A Ta2O5/silicon barrier height of 0.77 eV was extracted from the slope of the ln (IG/ID) versus ln (ISUB/ID) plot using the lucky electron model. Thermionic emission calculation gave a lower Ta2O5/silicon barrier height of 0.56 eV. These two models gave more consistent results when a new ionization energy Fi equal to the energy gap of silicon was used.
Negative transconductance effect in silicon-based MOSFETs fabricated with Ta2O5 gate dielectric was observed at room temperature. The negative transconductance effect was caused by the real-space-transfer of channel electrons similar to that in charge injection transistors (CHINT). The intrinsic Ta2O5/silicon electron barrier height FBO was calculated to be 0.51 eV from the gate current based on thermionic emission. The image force barrier lowering was about 0.14 eV for VDS ranging from 1.5 V to 4.0 V.
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