Concurrent-Simulation-Based Remote IP Evaluation over the Internet for System-on-a-Chip Design
碩士 === 國立清華大學 === 資訊工程學系 === 89 === We propose an Internet-based concurrent-simulation scheme to ease IP evaluation process between IP vendors and users. Complex system-on-a-chip design requires more and more IP modules from 3rd party vendors. What can be disclosed by the vendor without i...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/62099357871866450897 |
| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 89 === We propose an Internet-based concurrent-simulation scheme to ease IP evaluation process between IP vendors and users. Complex system-on-a-chip design requires more and more IP modules from 3rd party vendors. What can be disclosed by the vendor without impairing its trade secrete and what needs to been examined by the user to gain satisfactory level of confidence are contradictory of each other. Via PLI interface functions and Internet protocol, our proposed software enables HDL simulators (Verilog) residing in both the vendor and user’s sites to concurrently simulate the IP and SOC together. Only stimulus and response defined in the IP’s module I/O are exchanged between the sites. Therefore, the vendor need not to create a functional model (or encrypted code) for the IP while the user is assured what he/she simulates is what he will purchase. Beside simulation speed degradation due to communication overhead, the SOC design/debug process is exactly same as if the IP is in the user’s hand. Our contribution will help all IP providers expose their IPs to all potential users without human intervention and IP right infringement concern.
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