| Summary: | 碩士 === 國立東華大學 === 資訊工程學系 === 89 === A new VLSI design of a high-speed Reed-Solomon codec is
presented in this thesis. Reed-Solomon code is one of the most important error controlling codes in digital communication. It is especially powerful for multiple error correction, thus suitable for random and burst error correction. In this thesis, we propose a high-speed Reed-Solomon codec that can reduce the number of clock cycles in the pipeline stage, and thus resulting a more efficient structure.
In the thesis, a high-speed (252,236) Reed-Solomon codec is realized by VLSI implementation in a single chip. The error correcting function is programmable. The error correcting capability is up to 8 bytes. The Reed-Solomon codec only uses 28 finite field multipliers in the chip. It operates at a clock frequency of 50MHz and has a data processing rate of 1.5 Gbits/s in gate-level simulation. The chip consists of 75695 gates in 9.56 mm2 area with a TSMC 0.35um 1P4M Silicide technology. It had been passed through CIC investigative meeting. The chip is currently being fabricated in TSMC.
3
|
|---|
