An ASIC Design of the TCM Decoder for Gigabit Ethernet 1000 Base-T Transceiver
碩士 === 國立交通大學 === 電信工程系 === 89 === This thesis considers the trellis coded modulation (TCM) decoder design for the Gigabit Ethernet (1000 Base-T transceiver. The decoding scheme involves the well-known Viterbi algorithm. In the hardware implementation of the Viterbi decoder, an important...
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| Format: | Others |
| Language: | en_US |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/75817106842629420095 |
| Summary: | 碩士 === 國立交通大學 === 電信工程系 === 89 === This thesis considers the trellis coded modulation (TCM) decoder design for the Gigabit Ethernet (1000 Base-T transceiver. The decoding scheme involves the well-known Viterbi algorithm. In the hardware implementation of the Viterbi decoder, an important module is called survivor memory unit (SMU). Conventionally, the SMU of the 1000 Base-T Viterbi decoder is implemented using the register-exchage method (REM) which results in a large area and complex routing. In this thesis, we employ a new method called the register-trace-back (RTB) structure for ASIC design of TCM decoder. This method can effectively reduce the area and simplify the routing. Finally, the overall decoder design is realized using the VHDL hardware description language.
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