| Summary: | 博士 === 國立交通大學 === 電子工程系 === 89 === In this dissertation, the algorithm and architecture of memory-based VLC codec designs are presented. Systematic optimization procedures are proposed to reduce the memory requirements and increase the operation throughputs. Efficient compression and decompression schemes with full programmability are achieved for real applications in multimedia and communications.
This dissertation first presents an algorithm to predict the codeword-boundary in a single bitstream for breaking the recursive dependence of VLC decompression. Codelengths are known before decoding procedures are completed. Hence, a multi-processor architecture is used to deal with a single codeword bitstream and increase the decoding throughput. With this improvement, the VLC decoder can be utilized by most applications.
In order to simplify IO conditions and further enhance performance, a group-based VLC codec design with full table programmability is proposed. Both coding tables and symbols are loaded into memories because memory requirements are reduced significantly by a codeword grouping and symbol conversion. With parallel group searching, the VLC codec obtains a constant symbol rate, i.e. one symbol per clock cycle. Owing to that the group information is shared, concurrent encoding and decoding procedures are carried out. Consequently, this VLC codec design satisfies the requirements of high performance systems and interactive communications.
According to the group-based VLC codec scheme, a novel multi-table merging approach is developed to achieve multi-table programmability with a limited memory space. By the table merging methods, information redundancies among coding tables are explored and global memory requirement optimization is fulfilled. Then, the data of all used tables are stored in memories. Table changing is preformed by switching rather than reloading the memory contents. Since both memory space and table switching time are saved, an area efficient and high throughput memory-based VLC codec design is realized for practical applications, where the used table is changed frequently.
Employing the multi-table-merged VLC codec, a video decoder architecture is presented. Due to the memory-based VLD, the video decoder acquires the adaptability and programmability for various coding schemes. Because of efficient pipelining, the VLD module maintains the operation rate and processes one codeword per clock cycle. This video decoder is implemented in 0.35-mm CMOS technology. Simulation results show that the throughput of the proposed VLC decoder is up to 56.5M symbols/sec and the decompression rate of the video decoder is 400M pixels/sec with a clock rate of 66MHz. As a result, the proposed memory-based VLC codec is quite suitable for real application systems.
Finally, the design methodology used by the video decoder is described for reducing the complexity of function unit design and system integration. Additionally, the design guidelines of the memory-based VLC codec are discussed for reusing it in versatile applications and different system architectures.
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