| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 89 === With the rapid advance in CMOS technology, the trend of the VLSI design is then towards system-on-chip (SoC) where design methodology, cost, and turnaround time are major issues. Concepts of intellectual property (IP) are then proposed to fit for SoC designs. Based on a digital frequency synthesizer (DFS) controller IP, the wideband digital frequency synthesizer is proposed to fit in with the wireless LAN (local area network) applications, which provides low cost and efficient design periods. A full-custom voltage-controlled oscillator (VCO) is designed to achieve the system requirements and generate such a high-speed frequency.
In order to solve the interface between the DFS controller IP and the VCO and provide a digital-to-voltage conversion, a novel cell-based digital-to-voltage converter (DVC) is proposed, too. This DVC only uses inverters and tri-state inverters, which are common and various elements in a cell library. The cell-based manner gives a low-cost and portable design methodology of the digital-to-voltage conversion.
The wideband digital frequency synthesizer is fabricated in TSMC 0.35 mm single-poly-quadruple-metal (SPQM) CMOS technology. The measurement results show that its output bandwidth is from 136 MHz to 1.981 GHz and has a peak-to-peak jitter of 403 ps with root-mean-square (RMS) value of 85.6 ps @256 MHz. The DVC resolution can achieve 0.32 mV.
At last, a 1.8 GHz direct-convert DQPSK transmitter is proposed based on the architecture of wideband digital frequency synthesizer. The post-layout simulations show it not only achieves the properties of wideband digital frequency synthesizer but also chooses the proper output phase from baseband inputs, I and Q. This makes the application of wideband digital frequency more flexible and practical. It also reduces design turn-around time and increases efficiency in the SoC design indeed.
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