| Summary: | 博士 === 國立交通大學 === 電子工程系 === 89 === This dissertation explores the technology mapping problem for complex Field-Programmable Gate Arrays (FPGAs).
FPGAs have been widely used for implementing prototypes of ASICs for their short turnaround time. Complex FPGAs further support faster speed and higher density. Its architecture features hard-wired connections, non-homogeneous logic blocks, and limited accessible fanouts. This dissertation proposes two new technology mapping algorithms for optimizing for area and delay respectively.
In the area-driven algorithm, we use a multiple-fanout pattern graph library to model the complex logic block architecture and a pre-mapping technique to generate the subject graph dynamically. A new matching algorithm and a new covering algorithm are also developed for the subject graph covering.
In the delay-driven algorithm, we present a guaranteed delay optimal technology mapping algorithm for hard-wired non-homogeneous FPGAs. To handle the hard-wired features with traditional labeling-mapping algorithm, we propose a two-dimensional labeling approach and a complex node cut algorithm.
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