| Summary: | 博士 === 國立交通大學 === 電子工程系 === 89 === This dissertation explores the benefits and problems in public-key cryptosystems. Although the adoption of public-key cryptosystem can avoid some typical problems in conventional cryptosystems, the major problem of current public key cryptosystems is their significant computation complexity, which often limits the throughput rate of cryptographic computation. To implement the main operations of cryptosystems, a systolic array could be very suitable due to its inherent properties of pipelining, homogeneity, and localization. The pipelined architecture can be utilized to improve the throughput rate by shortening the clock period and the total processing time; The homogeneity property of systolic array may help the shortening of the design and testing period in VLSI implementation; and the property of spatial and temporal localization may be used to localize data transactions and control flow for smaller routing area and higher computation speed.
In this thesis, We proposed two approaches to design the systolic architectures: splitting method and merging method. In the partitioning method, the number of pipeline stages is increased and the clock cycle period is shortened. By adopting pre-computation, together with the parallelism of these pipelines, the computation speed of the partitioned structure can be improved. The merging method, on the other hand, may avoid the one-clock-cycle-gap problem and decrease the area size, power consumption, and complexity. This merged architecture can be further optimized for computation speed. These two proposed methods are adopted in the implementation of a Montgomery-based modular multiplier for RSA public-key cryptosystems and a finite-field multiplier for elliptic curve cryptosystems. The comparisons show that our partitioning method offers higher throughput rate while our merging method offers lower area size, lower power consumption, and lower complexity. Furthermore, for a farther stage of development, we generalize our two systolic architectures to handle more general operations. Among these designs which could be suitable for our generalized architectures, we mention a high-radix RSA public-key cryptosystem as an example. Moreover, due to the fact that the key length of a public key cryptosystem is usually long for security reason, it becomes fairly difficult to quickly estimate the actual power consumption of these long-bit systolic arrays. Hence, in this thesis, we also propose a new power estimator to handle the power estimation of long-bit systolic architectures.
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