| Summary: | 碩士 === 國立交通大學 === 資訊科學系 === 89 === Continued improvement in semiconductor process technology enables designer to put a complex system into a single chip. The so-called System-on-Chip (SoC) consist of application specific hardware components, processors, memory etc. Because of some functionalities will be implemented with software, hardware platform and embedded software should be developed together from starting point. This integration makes design of SoC difficult.
Considering System-on-Chip, system-level design plays an important role in the outcome of development. In this thesis, we draw main elements from a single chip personal digital assistant, and use Cadence® Virtual Component Co-Design environment to partition off whole system into hardware and software. With it’s help, we can make design decisions in hardware/software partitioning and hardware specification. We implemented a H.263 software codec. According to the estimation of final system performance and implementation complexity, we decide to implement the system with ARM9 and DSP cores as computing engines.
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