Design of Delay-Locked Loop Tracking Pseudonoise Code Circuit
碩士 === 國立成功大學 === 電機工程學系 === 89 === Pseudonoise code of synchronization is important part in direct-sequence spread-spectrum system design. It is used to synchronize between the transmitters and receivers with delay-lock loop. As is well-known, the synchronization entails two steps: acqui...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53937254396616534004 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 89 === Pseudonoise code of synchronization is important part in direct-sequence spread-spectrum system design. It is used to synchronize between the transmitters and receivers with delay-lock loop. As is well-known, the synchronization entails two steps: acquisition and tracking. There are some techniques that can be applied for code acquisition and tracking. Among them, we consider the serial search code acquisition and early late code tracking for synchronization. The main purpose of this thesis is to design all digital circuit with pseudonoise code of synchronization. The proposed circuit is designed with FPGA modules. With sixteen-time oversampling of the 1.25MHz chip rate, the circuit has been tested and proven to work at a speed of 20MHz.And the functionality of the circuit will be simulated.
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