| Summary: | 碩士 === 國立中興大學 === 電機工程學系 === 89 === As VLSI circuits migrate to high density, DRAM device technology advances to the deep sub-micron range. The small devices can meet the requirement of the high- speed and high-density, but many other problems degrade circuit performance or even invalidate the original design, especially the problem of the crosstalk effect of wires influencing the circuit performance is getting more seriously, so, it is necessary to develop a new crosstalk effect model to meet the trend.
The purpose of this thesis is to develop a new analytical delay model for read operation on DRAM bit lines. The compact expression combining accurate device models and distributed RC lines, as well as crosstalk of multiple bit lines for DRAM has been derived. The agreement between the compact model and SPICE simulation for 0.18mm technology is demonstrated. The impacts of the distance between the bit lines and the cell number on the bit line are presented. The circuit designers can use the model to compute the variation accurately and quickly on the DRAM bit lines with crosstalk effect.
|
|---|
