FPGA Design for Real-Time Spiral Magnetic Resonance Imaging

• Main Authors: Chuan-Yi Yu, 余權益
• Other Authors: Jan-Ray Liao
• Format: Others
• Language: zh-TW
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/22791247656884313935

碩士 === 國立中興大學 === 電機工程學系 === 89 === Magnetic resonance imaging (MRI) is a very versatile medical imaging tool. The main reasons are twofold. First, it can produce high-quality images. Second, and it has many imaging parameters that can be changed to fit different imaging needs. Because MRI requires a long process of exiting and receiving the nuclear magnetic resonance signal, the main hurdle for MRI today is its slow imaging speed. To overcome the problem, many fast imaging methods have been invented. Spiral MRI is one of these methods. Spiral imaging used a spiral trajectory to quickly cover a large portion of data so that the number of times required to excite the NMR signal is reduced. Therefore, it can finish much faster than other methods. Comparing to other fast imaging methods, the benefit of the spiral imaging is that it is insensitive to motion-related artifacts, because physiological motion is what we want to see in real-time imaging. The problem is that spiral trajectory does not acquire data at rectilinear grid and it is necessary to re-grid the acquired data before fast Fourier transform. This process is often also called “gridding”. This thesis describes an implementation of the gridding algorithm on Field Programmable Gate Arrary (FPGA) chip. The algorithm is written in hardware description language (HDL) and synthesized by computer-aided design (CAD) tools to reaches the goal of real-time reconstruction. FPGA Chips have the advantages of low cost and they are highly programmable for digital system design so that the system implementation time is reduced. The system architecture, we used is to store the reconstruction parameters on static random access memory (SRAM), and transmit the data to FPGA to reconstruct the images. The reconstructed results are stored on SRAM and transmitted back to personal computer for post processing. The HDL we used is Verilog. After simulation and synthesis, the codes are downloaded to FPGA chip to test its functions. To further validate of FPGA chip design, C++ and Matlab simulation are also performed .