Fault-Tolerant Techniques for High Capacity RAMs

• Main Authors: Chih-Hsien Hsu, 許志賢
• Other Authors: Shyue-Kung Lu
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/08832650718937887311

碩士 === 輔仁大學 === 電子工程學系 === 89 === The most commonly used redundancy technique for high-capacity RAMs is the inclusion of extra rows and columns. Hard cell failures and row/column failures can be repaired with this technique to improve yield and reliability. However, it is inefficient to use an entire row (column) to replace a faulty row (column), respectively. This situation is more severe if a faulty row (column) contains only few faulty memory cells. In this paper, we propose fault-tolerant memory (FTM) systems that can be used to replace the traditional redundancy strategies. Our FTM systems are based on divided bit-line (DBL) and divided word-line (DWL) structures. This paper is the first attempt to construct fault-tolerant memories by these concepts. A memory column (row), include the redundant column (row), is partitioned into column blocks (row blocks), respectively. If the replacement is performed at the row-block level, then a row block-based FTM (RBFTM) system is used. Alternately, if the replacement is performed at the column-block level, then a column block-based FTM (CBFTM) system is used. If both approaches are incorporated into a memory chip, then the hybrid FTM (HFTM) system is achieved. The storage and remapping of faulty addresses can be implemented with a CAM (content addressable memory) such that faulty blocks will not be referred. Besides, the characteristics of low power and fast access time of DBL and DWL memories are also preserved.