| Summary: | 碩士 === 逢甲大學 === 自動控制工程學系 === 89 === There are many efficient VLSI architectures of 2-D DCT and 2-D IDCT for area and processing speed points of view. However, most of them spend much cost for using in a real-time digital video codec system. The aim of our research work was to develop an area efficient and low complexity VLSI architecture of 2-D DCT and 2-D IDCT for real-time digital low bit-rate video codec system. Hardware cost and performance of this architecture are main key point. It is based on the row-column decomposition technique. This architecture would be shown that a single 1-D DCT/IDCT could take role of 2-D DCT and 2-D IDCT. It can be achieved through precise timing scheduled. Intuitively, three 1-D DCT/IDCT and a matrix transposition could be saved as compared to the conventional architectures which usually use two one-dimensional transforms and transposition memory. To reduce its processing time, the proposed architecture used 3-bit serial distributed arithmetic, parallel and pipelined method. We simulated the finite wordlength of the proposed 2-D DCT/IDCT algorithm with C language. Then, based on TSMC 0.35um process technique, Galax! 0.35um cell library is used to implement the 2-D DCT/IDCT architecture. In proposed architecture, 11895 gates were consumed roughly for 45 MHz operating clock. As a result, this architecture can be characterized to maximize the utilization of the hardware resources. It also can be applied to the ASIC chips for real-time digital low bit-rate video codec system and multimedia services especially requiring low cost and low hardware complexity.
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