| Summary: | 碩士 === 大葉大學 === 電機工程研究所 === 89 === At the phase of device design of MOSFET, the effective channel length is one of the most important parameters. It is also necessary to control the effective channel length ccording to the design during the manufacture of MOSFET. Due to the importance of the effective channel length for MOSFET,this thesis is focus on extracting the length of velocity saturation region, and it`s variation with different temperatures and substrate bias. Furthermore, the threshold voltage variation due to changes of the channel length, and the hot carrier effect are also discussed.
When device is operated on saturation regime, the maximum electric field of LDD structure is lower than conventional MOSFET in the same bias conditions, which influence the velocity of the carriers. With increasing gate bias voltage, the drain current will be increased, but Rtotal will be reduces. In this thesis we use the simple one order model for drain current, and utilize the Rtotal relation with drain current, we can extract the length of velocity saturation region.
First, we design MOSFET`s devices in different channel lengths, after that, we use the linearly extrapolated method to extract the threshold voltage from the MOSFET`s Ids-Vgs curve in different temperatures and substrate bias. At finally, we use that method extract Lsat parameters. Furthermore, we utilize simulations result from medici to prove experiment data. From experiment results, we will understand that, with increasing channel length and gate bias, the length of velocity saturation region will increase. With increasing temperature, it
will decrease.
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