| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 89 === To shorten time to market , the architecture , FPGA, is used widely. Because the circuit is larger and more complex, it is necessary to partition a large circuit to several sub-circuits. Although a FPGA is programmable, the chief shortcoming of FPGA is poor performance, so that many real time systems can not implemented by FPGAs, especially when we deal with the problem of FPGA partitioning, the performance problem is more serious. We will partition the circuit to several different FPGAs and the delay of the wires cross two FPGAs is larger. We hope to decrease the delay of the critical path to achieve the performance driven goal.
As the fabrication technology rapidly evolves, the FPGA with single resource is not enough, so the architecture of FPGA with complex resources is brought up. The Objective of our research is performance driven partitioning that partition the circuit to FPGAs with complex resources successfully with cost minimization.
When we partition the circuit, we do not increase the delay of the critical path as far as possible. In the results of the experiments, we can see the algorithm not only partition the circuit with cost minimization but also improve the performance of the partitioning.
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