| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 89 === Because of faster and faster broad bandwidth digital network, more various communication services can be implemented. The capability of multicast is important to support many services such as video conference. In the past IP Multicast was implemented by either Unicast or software therefore it usually becomes a bottleneck of the system. This thesis presents a high speed system architecture for processing data packet and control packet of IP Multicast which uses IGMP（Internet Group Management Protocol）and DVMRP（Distance Vector Multicast Routing Protocol）as communication protocol. We implemented this system by conception of embedded system.
In processing data packet, we use the type of shared buffer memory and the policy of Single Write Single Read to store and forward data. In searching multiple output ports, we construct a routing cache table by hardware. We use parallel CAM search circuit to provide searching and updating this table quickly. In processing control packet, it is hard to entire implement in hardware because complex judgment and more variation in communication protocol. We design a 8 bit embedded micro-processor to take care it. In real VLSI implementation, our design use CCU 0.25μm low power cell library and achieve simulation.
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