Mixed-model Pipeline Fast Fourier Transform Processor

• Main Authors: Yung-Chan Jiang, 江永權
• Other Authors: Ching-Wei Yeh
• Format: Others
• Language: zh-TW
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/73669081531548045224

碩士 === 國立中正大學 === 電機工程研究所 === 89 === The Fast Fourier Transform plays an important role in analysis, design, and implementation of discrete-time single processing algorithms and systems. In this thesis, we first introduced conventional FFT processor architecture. FFT processor is one of the key components in the implementation of wideband OFDM systems. Architectures with structured pipeline have been used to meet the fast, real-time processing demand and low-power consumption requirement in a wire or wireless environment. A VLSI oriented fast Fourier transform (FFT) algorithm — radix22, which can effectively minimize the number of complex multiplications. The algorithm can be implemented efficiently using a pipelined architecture. Based on this pipelined architecture, a variable- length FFT ASIC is designed for use in the DAB, DVB-T, ADSL and VDSL applications. In this thesis we present the implementation of multiplier base on a Cordic theory. In order to reduce the required chip area for the sequential processing of complex data complex multiplication contains four real multiplications are used. The proposed chip is fabricated using a 0.35　standard CMOS process. As the experimental results of the chip indicate, the FFT processor can operate 72MHz at 3.3V supply voltage.