Design of Highly Efficient VLSI Architecture for 2-D DWT and 2-D IDWT

• Main Authors: Yan-Sheng Li, 李延昇
• Other Authors: Yun-Nan Chang
• Format: Others
• Language: zh-TW
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/63555366679415931815

碩士 === 國立中正大學 === 資訊工程研究所 === 89 === With the rapid progress of VLSI design technologies, many processors based on audio and image signal processing have been developed recently. In this thesis, we present a design methodology for the implementation of high-performance 2-D discrete wavelet transform (DWT) and inverse DWT (IDWT). By exploiting the multi-rate feature inherent in the algorithms, an effective schedule that interleaves all the row-wise and column-wise computations of different octaves onto three fundamental convolutional filters is proposed. Based on this computation schedule, very high efficient architectures can be synthesized. The resulting architectures can not only achieve fast computation time at less silicon cost due to nearly full hardware utilization, but they are also simple and modular, making them very suitable for VLSI implementation. Furthermore the proposed design methodology enables the design of the configurable architecture that can process both DWT and IDWT.