Timing Driven Restructuring
碩士 === 國立中正大學 === 資訊工程研究所 === 89 === The purpose of logic synthesis is to derive a gate level implementation from the initial specification taking into account several design objectives in mind such as timing, area and power. There have been many timing optimization algorithms proposed pr...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/30037167376324587357 |