| Summary: | 博士 === 國立中正大學 === 資訊工程研究所 === 89 === Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design high-performance processors. However, domino logic suffers from several design problems and one of the most notable ones is the charge-sharing problem. Charge sharing which occurs in any CMOS domino gate may degrade the output voltage level or may even cause an erroneous output value. In this thesis, this problem is thoroughly investigated by considering circuit topology and circuit function. We describe a method to measure the sensitivity (called CS-vulnerability) of the charge-sharing (CS) problem for each domino gate. A method to derive the CS-vulnerability and the test vector for each domino gate is suggested. We also propose a transistor reordering method to dramatically reduce the CS-vulnerabilities for all domino gates, so that the CS problem can be alleviated. We also prove theoretically that a set of test vectors generated for single CS faults can also detect all multiple CS faults. This good property significantly guarantees the test quality for the CS faults of domino circuits. In this work, we also find that charge-sharing faults are extremely resistant to scan test. In fact, charge-sharing faults occurring at the border gates cannot be detected by any scan method, due to the missing error caused by early signal arrival time. Further, we show that killing error might happen in charge-sharing fault detection for both border gates and non-border gates because of the low-speed testing problem caused again by scan test. We thoroughly investigate both test errors and propose two design-for-testability techniques to efficiently eliminate both problems. To detect the worst-case charge-sharing faults, a two-pattern test technique is proposed, and the process of two-pattern test generation is also presented.
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