Low-Power and Low Phase-Error Phase-Locked Loop Design

• Main Authors: Lin-Jiunn Tzou, 鄒林俊
• Other Authors: Kuo-Hsing Cheng
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/09852958189496753741

碩士 === 淡江大學 === 電機工程學系 === 88 === Phase-locked loop (PLL) is the component broadly used in various field of integrated circuits. Phase-locked loop is generally used in clock recovery of communication system and frequency synthesizer of wireless communication system. Recently, owing to the broadly use of the mobile electronic systems , low power consumption has become the main concern in the modern VLSI design. With the progress of VLSI technology ,phase locked loop is necessarily designed in system on a chip in .Thus ,PLL has wide applications as well as operational amplifier does. Power consumption has become the main concern in moder VLSI because of the popuplar use of portable electronics .The goal of the paper is to design a low power phase-locked loop . In the conventional digital phase-locked loop, PLL contains Phase Detector, Charge Pump, Low Pass Filter, Voltage Controlled Oscillator and Frequency Divider. Voltage-controlled oscillator usually consumes a large portion of power in PLL, so it is necessary to design a low power voltage-controlled oscillator. Besides, phase error of the phase-locked loop is an important design consideration. Thus, the author use a “three-state” and small-dead-zone phase frequency detector[2] to reduce the phase error of the phase-locked loop. In the thesis, the author will complete a chip of the low-power and low phase -error phase locked loop working properly with 3V power supply based on UMC 0.5um technology .According to the Hspice simulation results, the most power consumption of DPLL is 7.93mW, the cycle jitter is between 21ps and 450ps and the long term jitter is between 50ps and 550ps. The results show a great reduction in power consumption and phase error.