The Implementation of A Novel DCT/IDCT Chip

• Main Authors: Chun-Pin Lin, 林俊賓
• Other Authors: Kuo-Hsing Cheng
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/25856889946127942021

碩士 === 淡江大學 === 電機工程學系 === 88 === The discrete cosine transform (DCT) is widely used in digital signal processing, particularly for digital image processing. Because of the complicated computational complexity, many efficient algorithms are proposed to improve the computing speed and hardware complexity. Discrete cosine transform (DCT) is used as core technique in the CODEC systems based on the compression standards of JPEG and MPEG. DCT can be implemented to integration circuits thanks to mature of semiconductor technology. The goal of this thesis is to design and implement a two-dimensional 8x8 discrete cosine transform chip for real-time applications. For real time application, this architecture of this DCT/IDCT chip contains the following features: (1) Modified butterfly architecture are applied to reduce a part of the adders, subtracters and multipliers. And make all coefficients of the modified butterfly architecture are positive to simplify the multiplier design. (2) Booth coding scheme and Wallace tree architecture are used to reduce the numbers of non-zero bit of coefficients and implementation the fast multiplier. (3) Pipelining architecture are applied to the parallel processing in order to reduce the total computing time efficiently.(4) Two transpose memory blocks are used to reduce the waiting state and to improve the latency. For 8x8 an information block, the latency only needs 37 clock cycles. The design is used Verilog HDL to implement the circuit modules and synthesis the modules with the cell library provided by CIC and synthesis tools provided by Synopsys. Then the Cadence CAD is used to do the auto-place-and-route (APR) and verification. Finally, transistor level simulation is analyzed with Timemill provided by EPIC.