The Design of a RSA Encryption/Decryption Circuit

• Main Authors: Chien-Cheng Chang, 張建誠
• Other Authors: 林銘波
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/61393486894775458082

碩士 === 國立臺灣科技大學 === 電子工程系 === 88 === The RSA encryption algorithm is widely used in communication and data security system. It takes much time to perform because of the RSA algorithm using more than 512-bit word lengths to guarantee security. Developing a high speed RSA encryption circuit which takes less gate count and can carry out its layout easily, will be a challenge. In this thesis, a 1024-bit RSA encryption circuit that is constructed by two 1024-bit adders is proposed. Based on the consideration of speed and regularity, a 1024-bit hierarchical carry skip adder consisting of 8 bits ripple adders is proposed. The adder only takes 9.4ns to perform a 1024-bit addition with 0.35μm SPQM cell library. The resulting RSA circuit can output a 10240-bit encrypted message every 22ms at the operating frequency of 72 MHz. Its die size is 3.7x3.7mm^2 and consumes 633mw. Moreover, the design of the proposed RSA circuit is modularized in a bit-sliced manner so that it can be expanded easily to a longer word length.