| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 88 === B-Splines and Non-Uniform Rational B-Splines (NURBS) have become the essential modeling primitives in computer graphics and geometric modeling applications. In this thesis, we propose a modified NURBS algorithm incorporated with two useful properties, sum up to one and dynamic denominator. This novel algorithm provides less order and fewer division operations than the traditional algorithm reported in the literature. Based on this algorithm, a unified architecture for the computation of various types of B-Spline curves and surfaces is presented. The resultant chip, consisting of approximately 752 K transistors, occupies 3.1 mm by 3.1 mm area in the 0.35-μm SPQM CMOS technology. It operates at 100 MHz with two 16-bit data outputs and consumes only 920mW at a supply voltage of 3.3V. The output data rate is two 16-bit words per cycle, which corresponds to a pair of the coordinate values of a point and its normal on a curve/surface.
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