| Summary: | 碩士 === 國立臺灣科技大學 === 資訊工程研究所 === 88 === Give n values x1, x2,..., xn and an associative binary operation , the prefix operation is to compute x1 x2 ...xi, 1 ≦ i ≦ n. Because prefix computation has many applications, a large number of combinational circuits, called prefix circuits, have been designed to solve the prefix problem. The depth d(D(n)) and the size s(D(n)) of an n-input prefix circuit D(n) satisfy the inequality d(D(n)) + s(D(n)) ≧2n - 2; thus, the prefix circuit is depth-size optimal if d(D(n)) + s(D(n)) = 2n - 2. A prefix circuit with a smaller depth is usually faster, and one with a smaller size usually requires less VLSI area. Moreover, a node with a smaller fan-out is faster and smaller in VLSI implementation. The size, depth, and fan-out of a prefix circuit should be as small as possible. For prefix circuits with the same fan-out, a circuit with a smaller depth should be faster. In this thesis, we construct a depth-size optimal parallel prefix circuit H4(n) with fan-out 4; the depth of H4(n) is the smallest of all known prefix circuits with bounded fan-out. We also present a new layout scheme for prefix circuits; when it applies to a depth-size optimal prefix circuit, the layout area is the smallest.
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