| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 88 === A low IF baseband transceiver VLSI architecture for high-speed digital communication systems over constrained-bandwidth channels will be presented in this thesis. At the transmitter end, an all-digital modulator is to perform QAM modulation. After a digital-to-analog converter (DAC), the continuous signal, which is located at low-IF band, is upconverted to the appropriate RF band for transmission.
Usually, the bandwidth-constrained channels induce harmful intersymbol interference (ISI). In order to overcome the harmful ISI, a fractionally spaced adaptive equalizer is employed for the QAM system to achieve the superior performance and relax the load of timing recovery at the receiver end. According to the feature of digital TV broadcasting which prefers to use life data to update the digital equalizer coefficients, a multi-stage LMS-based blind equalization algorithm is employed. Besides, taking the advantage of the fractionally spaced equalizer, the symbol rate timing recovery is realized. To reduce the hardware cost of the high-definition television (HDTV) equalizers, a pipelined architecture, which processes some parallel parts sequentially is realized. The synthesis results by hardware description language (HDL) show that the proposed architecture reduces the hardware complexity by a factor of four, compared with the architecture designed directly from the equalization algorithms. Moreover, a high hardware efficiency architecture of the pulse shaping filter is proposed, which reduces the hardware complexity by factor of four, compared with the architecture designed directly from the transfer function.
For carrier recovery, providing both wide lock-in range in the acquisition state and high jitter performance in the steady state is really hard to be realized in a simple architecture. A multi-stage dual-loop carrier recovery is proposed to satisfy the requirement. Taking advantages of particular loops cooperating with the non-decision-directed algorithm, the fractionally spaced equalizer, and the decision feedback equalizer (DFE) well, the carrier recovery can recover the received signal even the carrier frequency offset is more than 25000ppm and suppress the carrier jitter less than —82dB in the steady state. Besides, modifying carrier phase estimation algorithms can merge the two loops in a single-loop architecture. Both the hardware efficiency and high performance are achieved.
In order to testify the QAM transceiver system, the architecture provides 32.28Mbps gross bit rate using conventional NTSC 6MHz bandwidth is proposed for the digital CATV modem to solve the last-mile bandwidth bottleneck of local access for broadband services. Based on the proposed dual-loop carrier recovery, the full system can be conducted under the conditions of 100kHz carrier frequency offset, -82dB carrier jitter at 10kHz away from the carrier frequency. Due to the fractionally spaced equalizer, the decision-directed timing recovery can generate the timing tone for the ADC to sample the received signal properly, when the symbol timing offset is between 200ppm symbol rate offset. The simulation results show that the proposed VLSI architecture of the receiver has more than 30dB SNR of the equalized signal. Besides, the QAM baseband transceiver system is implemented with 0.35 TSMC on a single chip. The system clock rate is 43.03MHz and the chip area is 6.5×6.5mm2.
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