The Design and Realization of A Timing Generator Circuit for High Speed Automatic Test Equipment

碩士 === 國立臺灣大學 === 電機工程學研究所 === 88 === The heart of Automatic Test Equipment(ATE)is the timing generation circuitry. The timing generators are used to format the stimulus for the Device Under Test(DUT)and determine when to compare the device outputs against expect data. A CMOS implementation is parti...

Full description

Bibliographic Details
Main Authors: Yu-Chuan,Lin, 林有銓
Other Authors: 曹恆偉
Format: Others
Language:zh-TW
Published: 2000
Online Access:http://ndltd.ncl.edu.tw/handle/00687939790240446217
id ndltd-TW-088NTU00442097
record_format oai_dc
spelling ndltd-TW-088NTU004420972016-01-29T04:18:38Z http://ndltd.ncl.edu.tw/handle/00687939790240446217 The Design and Realization of A Timing Generator Circuit for High Speed Automatic Test Equipment 應用於高速自動測試儀器之時序產生器電路設計與製作 Yu-Chuan,Lin 林有銓 碩士 國立臺灣大學 電機工程學研究所 88 The heart of Automatic Test Equipment(ATE)is the timing generation circuitry. The timing generators are used to format the stimulus for the Device Under Test(DUT)and determine when to compare the device outputs against expect data. A CMOS implementation is particular diffcult because of the high data rate and accuracy requirements of ATE timing generator. In this thesis, several timing generator architectures will be introduced. A timing generator is divided into two parts according to the delay time resolution. The first part, coarse timing generator, based on down counter circuitry design. The second part, fine timing generator, composed by a series of delay units and multiplexers. To obtain well defined delay time independent of variations in process , supply voltage and temperature, delay units are controlled by a voltage derived by dual delayed locked loops (DLL), which are synchronized to an 100MHz external reference clock. A first version of the chip was developed to a fine timing generator. The delay resolution is 50ps and the range is above 10ns. It was fabricated in TSMC 0.35um 1P4M CMOS technology. The measurement results are in the following: DNL is —0.5LSB~+0.5LSB and INL is —2.5LSB~+2LSB when the timeset unit is 200ps. The measured RMS jitter of timing generator is under 20ps, peak to peak jitter is under 170ps. 曹恆偉 2000 學位論文 ; thesis 101 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立臺灣大學 === 電機工程學研究所 === 88 === The heart of Automatic Test Equipment(ATE)is the timing generation circuitry. The timing generators are used to format the stimulus for the Device Under Test(DUT)and determine when to compare the device outputs against expect data. A CMOS implementation is particular diffcult because of the high data rate and accuracy requirements of ATE timing generator. In this thesis, several timing generator architectures will be introduced. A timing generator is divided into two parts according to the delay time resolution. The first part, coarse timing generator, based on down counter circuitry design. The second part, fine timing generator, composed by a series of delay units and multiplexers. To obtain well defined delay time independent of variations in process , supply voltage and temperature, delay units are controlled by a voltage derived by dual delayed locked loops (DLL), which are synchronized to an 100MHz external reference clock. A first version of the chip was developed to a fine timing generator. The delay resolution is 50ps and the range is above 10ns. It was fabricated in TSMC 0.35um 1P4M CMOS technology. The measurement results are in the following: DNL is —0.5LSB~+0.5LSB and INL is —2.5LSB~+2LSB when the timeset unit is 200ps. The measured RMS jitter of timing generator is under 20ps, peak to peak jitter is under 170ps.
author2 曹恆偉
author_facet 曹恆偉
Yu-Chuan,Lin
林有銓
author Yu-Chuan,Lin
林有銓
spellingShingle Yu-Chuan,Lin
林有銓
The Design and Realization of A Timing Generator Circuit for High Speed Automatic Test Equipment
author_sort Yu-Chuan,Lin
title The Design and Realization of A Timing Generator Circuit for High Speed Automatic Test Equipment
title_short The Design and Realization of A Timing Generator Circuit for High Speed Automatic Test Equipment
title_full The Design and Realization of A Timing Generator Circuit for High Speed Automatic Test Equipment
title_fullStr The Design and Realization of A Timing Generator Circuit for High Speed Automatic Test Equipment
title_full_unstemmed The Design and Realization of A Timing Generator Circuit for High Speed Automatic Test Equipment
title_sort design and realization of a timing generator circuit for high speed automatic test equipment
publishDate 2000
url http://ndltd.ncl.edu.tw/handle/00687939790240446217
work_keys_str_mv AT yuchuanlin thedesignandrealizationofatiminggeneratorcircuitforhighspeedautomatictestequipment
AT línyǒuquán thedesignandrealizationofatiminggeneratorcircuitforhighspeedautomatictestequipment
AT yuchuanlin yīngyòngyúgāosùzìdòngcèshìyíqìzhīshíxùchǎnshēngqìdiànlùshèjìyǔzhìzuò
AT línyǒuquán yīngyòngyúgāosùzìdòngcèshìyíqìzhīshíxùchǎnshēngqìdiànlùshèjìyǔzhìzuò
AT yuchuanlin designandrealizationofatiminggeneratorcircuitforhighspeedautomatictestequipment
AT línyǒuquán designandrealizationofatiminggeneratorcircuitforhighspeedautomatictestequipment
_version_ 1718167532807913472