| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 88 === The heart of Automatic Test Equipment（ATE）is the timing generation circuitry. The timing generators are used to format the stimulus for the Device Under Test（DUT）and determine when to compare the device outputs against expect data. A CMOS implementation is particular diffcult because of the high data rate and accuracy requirements of ATE timing generator.
In this thesis, several timing generator architectures will be introduced. A timing generator is divided into two parts according to the delay time resolution. The first part, coarse timing generator, based on down counter circuitry design. The second part, fine timing generator, composed by a series of delay units and multiplexers. To obtain well defined delay time independent of variations in process , supply voltage and temperature, delay units are controlled by a voltage derived by dual delayed locked loops （DLL）, which are synchronized to an 100MHz external reference clock.
A first version of the chip was developed to a fine timing generator. The delay resolution is 50ps and the range is above 10ns. It was fabricated in TSMC 0.35um 1P4M CMOS technology. The measurement results are in the following: DNL is —0.5LSB~+0.5LSB and INL is —2.5LSB~+2LSB when the timeset unit is 200ps.
The measured RMS jitter of timing generator is under 20ps, peak to peak jitter is under 170ps.
|
|---|
