| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 88 === In last few years, the remarkable growth in the personal wireless communications has motivated great interests in monolithic CMOS transceivers. Therefore, to implement a high efficiency power amplifier in a standard CMOS technology is one of the important challenges in the transceiver integration. In this thesis, the design and implementation of a power amplifier are described.
However, the implementation of CMOS power amplifiers suffers from many disadvantages of the intrinsic CMOS characteristics. The handicaps include insufficiency driving capability, low breakdown voltage, large parasitic capacitors, and lossy substrate. Therefore, we have to introduce a different approach from the standard way, which is used to design GaAs or bipolar power amplifiers.
We have investigated a switching class E approach, which can achieve higher efficiency than traditional classification of power amplifiers. A fully differential topology and the composite switch technique are presented to alleviate the problems of CMOS. A facile power control node is also created for the linearization system. In addition, a low insertion loss and broad bandwidth lumped element hybrid is implemented to convert the signal between signal-ended and differential. The thesis is successful to design and implement a 1-GHz, 162-mW power amplifier in TSMC 0.35-mm CMOS technology. The simulation and measurement results are also detailed in this thesis.
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