A Digital Signal Processor With Programmable Correlator Array Architecture For 3rd Generation Wireless Communication System
碩士 === 國立臺灣大學 === 電機工程學研究所 === 88 === In this thesis, a digital signal processor that is designed for communication appli-cations with a programmable correlator array architecture is introduced. The pro-grammable correlator can be easily configured as a chip match filter, code...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72755717795514800593 |