Job Shop Scheduling IC Design and Implementation

• Main Authors: Kuan-Hung Chen, 陳冠宏
• Other Authors: Shi-Chung Chang
• Format: Others
• Language: en_US
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/73535191476225202785

碩士 === 國立臺灣大學 === 電機工程學研究所 === 88 === Scheduling determines when to do what using which resource. A good scheduling is critical to the competitiveness of a manufacturer. Job shop is a typical environment for the manufacture of low-volume and high-variety parts, where parts are of various due dates, priorities and sequences of production operations. The underlying class of scheduling problems also appears in other applications such as multi-processor computing and communication packet routing. Among the existing algorithms for solving job shop scheduling problems, the Lagrangian relaxation neural network algorithm (LRNNA) developed by Luh et al., 1998, is an approach with quantifiable quality and successful industrial applications. It combines the Lagrangian relaxation, dynamic programming, and neural network-based optimization techniques. In LRNNA, the scheduling problem is decomposed, by applying Lagrangian relaxation, into neuron-based dynamic programming (NBDP) subproblems, where a dynamic programming procedure is mapped to an architecture of state neurons, comparison neurons, and interconnections between the two types of neurons. The Lagrangian multipliers for relaxation are stored in the Lagrangian neurons and updated by the subgradient information calculated from NBDP solutions. In this thesis, we design a VLSI implementation of LRNNA to speed up its solution finding. We first determine modifications of LRNNA algorithm needed for VLSI implementation by using software simulations. General multiplication operations are removed from the LRNNA algorithm and a 16-bit word length is selected. A baseline hardware architecture is then designed, which includes functional modules of state cells, a forward sweep circuit, an instruction decoder, a global memory, and two buses. State cells form a parallel processing architecture for arithmetic operations of LRNNA such as the cost calculation by the state neurons, the cost comparison by the comparison neurons, the calculation of subgradient information, and the multipliers updating. The design of one arithmetic operation unit in each state cell minimizes the hardware redundancy in arithmetic operations. The forward sweep circuit performs the forward sweep procedure in NBDP, which sequentially interacts with individual state cells. Global data such as due date and problem dimension parameters can be read from and written into the global memory via the global bus. The instruction decoder decodes instruction code to control the operations of modules in the architecture via the control bus. Expected improvements of speed performance are mainly due to parallel computations by state cells. To implement the proposed architecture, we conduct an iterative design of the detailed circuitry and a corresponding instruction set. By the analysis of the LRNN algorithm, basic arithmetic instructions and data transfer instructions are first proposed to implement the required arithmetic operations. To facilitate parallel computation, instructions that concurrently execute an arithmetic operation and the corresponding data transfer (between state cells) operation and instructions that contain an arithmetic operation and a sub-function depending on the results of the arithmetic operations are then proposed. The design of these instructions allow the algorithm to be implemented in minimum number of instructions and therefore minimizes the required clock cycle time needed. We implement the detailed circuit design based on the instruction set. Correctness of the circuit design is verified via simulations of problem solving and then translated into the physical layout by the standard-cell design procedures. After extensive verification of the functional and timing correctness of the layout, it is fabricated into a chip. Preliminary test results of the resultant chip show that it is functionally correct under the 3.3V supply voltage at 100MHz operating frequency with a power dissipation of 742.5 mW. The speed performance analysis of the chip indicates a potential of two orders of magnitude in speedup for the job shop scheduling problem solving than using software implementation.