| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 88 === The research of this thesis is focused to solve the signaling and timing problems encountered in high speed data links.
In chapter 2, some basic issues for the link are taken into consideration first. What are involved range from the fundamental concern of signal integrity to the systematic timing architecture.
In chapter 3, an easy and fast approach to characterize the wire medium, the 4.5m long IEEE 1394 Shielded-Twisted-Pair, is provided. The fitted lump circuit model is of great help for HSPICE simulation. With this cable model, two kinds of interface circuits are designed and verified by experimental results. One is called current mode transceiver because its transmitter is with the source-follower topology and its receiver is a common gate amplifier. The other is an integrating type receiver which periodically integrate, sample/hold and latch the input signal. Both of them are capable to transmit and/or receive GHz bit streams.
In chapter 4, a PWM (Pulse-Width-Modulation) signaling method is presented to alleviate the task of conventional clock recovery. The PWM symbol guarantees periodic rising edge such that the receiver could easily recover the clock simply by a PLL (Phase-Locked-Loop). The annoying data length problem is hence removed completely. The designed symbol rate is 200MHz which corresponds to an equivalent data rate is 400Mbps. By experimental results, the recovered clock has a peak-to-peak jitter of 106psec @ 200MHz, and the bit error rate is less than 5*10-5. The occupied die area is 823um*481um for the transmitter and 678um*338um for the receiver. The total power consumed is 120.5mW under a supply of 2.5V.
In chapter 5, different from the clock recovery, a source synchronous system employing SBTL (Simultaneous-Bidirectional-Transceiver-Logic) is designed. The SBTL is extended to be of 2 bits per symbol. That results in 4 amplitude quantization levels unidirectionally and total 7 for both directions. As for the source synchronous clock, it is buffered and deskewed by the DLL (Delay-Locked-Loop) and is used to retime the input stream. The simulation results unveil that a transfer rate of 1Gbps per wire is achievable. The transmitted clock rate is only 125MHz that is only 1/8 of the wire bandwidth.
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