Design of a high-resolution oversampling delta-sigma analog-to-digital converter with 2-2 MASH architacture

碩士 === 國立海洋大學 === 電機工程學系 === 88 === Abstract In this thesis, we propose a method that designs a high resolution oversampling Sigma-Delta analog-to-digital converter. The entire analog-to-digital converter contains two sections : an analog modulator and a digital filter. In the...

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Bibliographic Details
Main Author: 魏志璋
Other Authors: 劉 萬 榮
Format: Others
Language:zh-TW
Published: 2000
Online Access:http://ndltd.ncl.edu.tw/handle/77819015667371589546
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Summary:碩士 === 國立海洋大學 === 電機工程學系 === 88 === Abstract In this thesis, we propose a method that designs a high resolution oversampling Sigma-Delta analog-to-digital converter. The entire analog-to-digital converter contains two sections : an analog modulator and a digital filter. In the design of modulator, we take that multi-stage noise shaping with high order(four order) and high oversampling ratio (128) to improve the performance of the modulator. In circuit implement stage, we use the technology of fully differential switched-capacitor to accomplish the modulator. In digital filter part, we try the way of multiplierless to implement the filter. The analog-to- digital converter is designed to achieve above 20-bit resolution with signal bandwidth of 20kHz in baseband. The system sampling frequency is 6.144MHz, the oversampling ratio is 128, the signal-to-noise ratio is above 120dB. The total static power dissipation is 62mw and layout area is 990um * 810um for the analog modulator. The fabrication technology is UMC 5V 0.5um 2P2M technology.