A Low-Latency MARCH-Based Memory Repair Analysis Architecture
碩士 === 國立清華大學 === 電機工程學系 === 88 === The most important factors of repair analysis for embedded memory are area and speed. On the area point, a repair analysis usually requires a large space to store the fault information, and such large area in an embedded system is impossible. On the s...
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| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65419260565261127371 |
| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 88 === The most important factors of repair analysis for embedded memory are area and speed. On the area point, a repair analysis usually requires a large space to store the fault information, and such large area in an embedded system is impossible. On the speed point, the repair solution must designed quickly in order to reduce the overall testing time.
A memory repair analysis architecture for embedded memories is proposed in this thesis. This architecture runs at the speed of the BIST without disturbing the BIST operations and provides high repair rate for large amount of random repairable faulty cells
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