The Analysis of Multistage Switching Network with Shared Queue
碩士 === 國立清華大學 === 電機工程學系 === 88 === In order to achieve better performance of high-speed computer systems, the construction of high-speed communication infrastructure is needed. The infrastructures of network switches have deep influence on the performance of latency and bandwidth. To imp...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95440135800047137939 |
| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 88 === In order to achieve better performance of high-speed computer systems, the construction of high-speed communication infrastructure is needed. The infrastructures of network switches have deep influence on the performance of latency and bandwidth. To implement a network switch with better performance is not a straightforward work and may be a time-consuming process. Using the methods of simulation to perform the analysis of a switching network can reduce the work needed when constructing a real interconnection network. The objective of this thesis is to implement a simulator to analyze the behavior of switching network, including the impacts caused by the size of central queue and traffic skew. The average time of transferring data is discussed in this thesis to show the results of analyzing multistage interconnection network.
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